Design and analysis of Compressor Based Area-Efficient, High-speed Low-Power Multiplier

  • laxmi basgonda 
Keywords: Half adder, Full adder, compressor, Vedic multiplier, Low-power and High-speed


Multiplication is the basic arithmetic operation that is important in several microprocessors and digital signal-processing applications. Microprocessors use multipliers within their arithmetic logic units, and digital signal processing systems require multipliers to implement DSP algorithms such as convolution and filtering. Multipliers being the most area and power-consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, a multiplier based on an ancient Vedic mathematics technique has been proposed which employs 4:3, 5:3, 6:3, and 7:3 compressors for the addition of partial products. Combining the Vedic multiplier and efficient compressors, a robust area and power-efficient multiplier architecture has been achieved. The designs were synthesized and analyzed in Cadence Virtuoso in 180 nm technology. When compared with the previous compressor-based multiplier, the proposed design achieves a reduction in power and area respectively.


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Author Biography


SL Grade Lecturer, Electronics and Communication Engineering,
Dr. GSMR Polytechnic Kuknoor, Karnataka


[1]Swee, K. L. S. , Lo Hai Hiung, ”Performance Comparison Review of 32-Bit Multiplier Designs”, 4th International Conference on Intelligent and Advanced Systems (ICIAS), 2012 , IEEE proc. , vol. 2, pp 836-841

[2] H.D. Tiwari, et al., "Multiplier design based on ancient Indian Vedic Mathematics", Int. SoC Design Conf., 2008, vol. 2. IEEE Proc.,pp. II-65 - II-68.

[3] L. Sriraman, T.N. Prabakar, “Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics,” 1st Int. Conf. on Recent Advances in Information Technology, Dhanbad, India, 2012, IEEE Proc., pp. 782-787.

[4] S. R. Huddar, S. R. Rupanagudi, Kalpana M. ,S. Mohan : “Novel High Speed Vedic Mathematics Multiplier Using Compressors”, International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing 2013 ,IEEE proc. , pp. 465-469.

[5] D. Radhakrishnan and A. P. Preethy, "Low power CMOS pass logic 4-2 compressor for high-speed multiplication," Circuits and Systems, Proc. 43rd IEEE Midwest Symp., vol. 3, pp. 1296-1298, 2000.

[6] K.Prasad, K.K. Parhi, “Low power 4-2 and 5-2 compressors”, 35th Asilomar Conference on Signals, Systems and Computers, 2001, IEEE proc. vol.1, pp. 129 - 133

[7] A. Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyaya: “A 1.2-ns 16×16-bit Binary Multiplier using High Speed Compressors”, International Journal of Electrical, Computer and Systems Engineering, Vol. 4, No. 3, 2010, pp. 234 – 239

[8] W.J. Townsend, E.E. Swartzlander Jr., and J.A. Abraham , “A Comparison of Dadda and Wallace Multiplier Delays,” Proc. SPIE, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, pp. 552-560, 2003.

[9] B.Ramkumar, Harish M Kittur and P.Mahesh Kannan, “ASIC implementation of Modified Faster Carry Save Adder”, European Journal of Scientific Research, vol.42, pp.53-58, 2010.
How to Cite
basgonda , laxmi, & AMARESH M. (2018). Design and analysis of Compressor Based Area-Efficient, High-speed Low-Power Multiplier. IJRDO - Journal of Electrical And Electronics Engineering, 4(1), 6-10.