Interleaving Test Algorithm for Detecting Defects in DRAM

  • Anitha K Bannari Amman Institute of Technology
  • Sampath P Bannari Amman Institute of Technology
DOI: https://doi.org/10.53555/eee.v1i4.392
Keywords: Bit-line stress time, maximum stress time, sub threshold leakage-current defect, test algorithm.

Abstract

Since the minimum feature size of dynamic RAM has been down-scaled. Several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells and correct it due to the subthreshold leakage current.

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Author Biographies

Anitha K, Bannari Amman Institute of Technology

Department of Electronics and Cmmunication Engineering,

Sampath P, Bannari Amman Institute of Technology

Department of Electronics and Communication Engineering

Published
2015-04-30
How to Cite
K, A., & P, S. (2015). Interleaving Test Algorithm for Detecting Defects in DRAM. IJRDO - Journal of Electrical And Electronics Engineering, 1(4). https://doi.org/10.53555/eee.v1i4.392
Issue
Vol. 1 No. 4 (2015): IJRDO - Journal of Electrical And Electronics Engineering
Section
Articles

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